A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors

Author

Jan, C.-H. ; Bai, P. ; Choi, J. ; Curello, G. ; Jacobs, S. ; Jeong, J. ; Johnson, K. ; Jones, D. ; Klopcic, S. ; Lin, J. ; Lindert, N. ; Lio, A. ; Natarajan, S. ; Neirynck, J. ; Packan, P. ; Park, J. ; Post, I. ; Patel, M. ; Ramey, S. ; Reese, P. ; Rockfo

Author_Institution

Logic Technol. Dev., Intel Corp., Hillsboro, OR

fYear

2005

fDate

5-5 Dec. 2005

Firstpage

60

Lastpage

63

Abstract

A leading edge 65nm logic process technology employing uni-axial strained silicon transistors has been optimized for ultra low power products. Record PMOS/NMOS drive currents of 0.38/0.66 mA/mum, respectively, have been achieved at 1.2V and off-state leakage of 100 pA/mum. Greater than 1000times reduction of SRAM cell standby leakage through implementation of sleep transistors and other leakage suppression schemes are also discussed

Keywords

MOS logic circuits; MOSFET; SRAM chips; low-power electronics; 1.2 V; NMOS drive currents; PMOS drive currents; SRAM cell standby leakage; leakage suppression; logic platform technology; sleep transistors; uniaxial strained silicon transistors; Gate leakage; Handheld computers; Implants; Jacobian matrices; Logic; MOS devices; Random access memory; Silicon; Sleep; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International

Conference_Location

Washington, DC

Print_ISBN

0-7803-9268-X

Type

conf

DOI

10.1109/IEDM.2005.1609266

Filename

1609266