Title :
A 0.7 μm CMOS clock recovery circuit for 622 Mb/s SDH systems
Author :
de Vasconcelos, Eduardo ; Aguiar, Rui ; Santos, Dinis M.
Author_Institution :
Inst. de Telecomunicacoes, Campus Univ., Aveiro, Portugal
Abstract :
A clock recovery circuit for SDH STM-4 applications is described. The circuit has been implemented in a 0.7 μm CMOS technology. A digital VCO has been designed for the 622 MHz frequency. The chip sustained working frequencies from 550 up to 700 MHz. The recovered clock jitter (peak-to-peak) is under 150 ps, for SDH STM-4 data signals
Keywords :
CMOS digital integrated circuits; data communication equipment; digital communication; high-speed integrated circuits; optical communication equipment; synchronisation; synchronous digital hierarchy; timing circuits; timing jitter; 0.7 micron; 550 to 700 MHz; 622 Mbit/s; CMOS clock recovery circuit; SDH systems; STM-4 data signals; clock jitter; digital VCO; CMOS technology; Circuits; Clocks; Detectors; Flip-flops; Phase detection; Phase locked loops; Synchronous digital hierarchy; Voltage control; Voltage-controlled oscillators;
Conference_Titel :
Electronics, Circuits and Systems, 1998 IEEE International Conference on
Conference_Location :
Lisboa
Print_ISBN :
0-7803-5008-1
DOI :
10.1109/ICECS.1998.814019
