An experimental comparison of different approaches to ROM BIST

Author

Barbagallo, S. ; Burri, A. ; Medina, D. ; Camurati, P. ; Prinetto, P. ; Reorda, M. Sonza

Author_Institution

ITALTEL SIT CLTE-PA, Milan, Italy

fYear

1991

fDate

13-16 May 1991

Firstpage

567

Lastpage

571

Abstract

The issue of ROM testing in VLSI circuits is examined. The BIST (built-in-self-test) solution overcomes controllability and observability difficulties which represent the limits of conventional ATPGs (automatic test pattern generators) and becomes particularly suitable for deeply embedded ROMs. The classical approach is studied, and a novel solution which tries to minimize the masking effect of faults in the additional external logic is proposed. Preliminary results are also reported, related to some BIST implementations of ROMs with different dimensions, and the area overhead due to the BIST logic is carefully evaluated. A macro generator which produces the BIST block without any intervention of the IC designer, starting from ROM characteristics, is presented

Keywords

VLSI; automatic testing; built-in self test; controllability; integrated circuit testing; integrated memory circuits; logic testing; macros; observability; read-only storage; ROM testing; VLSI circuits; area overhead; automatic test pattern generators; built-in-self-test; controllability; deeply embedded ROMs; external logic; fault masking effect minimization; macro generator; observability; Built-in self-test; Character generation; Circuit faults; Circuit testing; Controllability; Logic; Observability; Read only memory; Test pattern generators; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

CompEuro '91. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference. Proceedings.

Conference_Location

Bologna

Print_ISBN

0-8186-2141-9

Type

conf

DOI

10.1109/CMPEUR.1991.257450

Filename

257450