• DocumentCode
    34408
  • Title

    Partially Parallel Encoder Architecture for Long Polar Codes

  • Author

    Hoyoung Yoo ; In-Cheol Park

  • Author_Institution
    Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
  • Volume
    62
  • Issue
    3
  • fYear
    2015
  • fDate
    Mar-15
  • Firstpage
    306
  • Lastpage
    310
  • Abstract
    Due to the channel achieving property, the polar code has become one of the most favorable error-correcting codes. As the polar code achieves the property asymptotically, however, it should be long enough to have a good error-correcting performance. Although the previous fully parallel encoder is intuitive and easy to implement, it is not suitable for long polar codes because of the huge hardware complexity required. In this brief, we analyze the encoding process in the viewpoint of very-large-scale integration implementation and propose a new efficient encoder architecture that is adequate for long polar codes and effective in alleviating the hardware complexity. As the proposed encoder allows high-throughput encoding with small hardware complexity, it can be systematically applied to the design of any polar code and to any level of parallelism.
  • Keywords
    error correction codes; parallel architectures; encoding process; error correcting codes; hardware complexity; long polar codes; partially parallel encoder architecture; very-large-scale integration implementation; Complexity theory; Computer architecture; Decoding; Delays; Encoding; Hardware; Registers; Polar codes; VLSI optimization; polar encoder; very-large-scale integration (VLSI) optimization;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems II: Express Briefs, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1549-7747
  • Type

    jour

  • DOI
    10.1109/TCSII.2014.2369131
  • Filename
    6951410