Technology mapping of digital circuits

Technology mapping aims to achieve minimal area or minimal delay circuits. The problem is computationally hard. Rule-based methods and heuristic algorithms have been applied. The algorithms rely on two important tasks, namely, matching and covering. Matching detects if a portion of a network can be implemented by a library element. Matching can be based on structural or on Boolean operations. Covering consists of choosing an appropriate set of matched elements that implement the original network and that optimize the overall area and/or delay. The major approaches to technology mapping are reviewed, with an emphasis on the recent results achieved by Boolean matching methods that can exploit the don´t-care conditions of a network. Specialized technology mappers that deal with functional-cell and programmable gate array libraries are described