An ASIC for image processing applications based on internal and external parallelism

A chip performing the special task of thinning is presented. Thinning, a common task in the field of image processing, preserves the overall structure of the image while making lines thinner and pixel spots smaller. Whereas thinning is normally only available on special image processing architectures in real time or is implemented in slow software, this ASIC solution makes thinning (at real-time conditions) available for general-purpose environments. This paper describes how parallelism is used to meet real-time constraints of the environment and how the ASIC can be integrated into an image processing pipeline. The results, and the layout of the chip, and some new ideas concerning testability aspects are presented