Title :
High performance distributed arithmetic FPGA decimators for video-frequency applications
Author :
Living, J. ; Al-Hashimi, B.M. ; Moniri, M.
Author_Institution :
Sch. of Eng. & Adv. Technol., Staffordshire Univ., Stafford, UK
Abstract :
This paper describes a method of implementing high performance integer decimators for video-frequency applications using FPGAs. The decimators are derived from polyphase decomposition of an FIR filter prototype and implemented using a modified distributed arithmetic look-up-table architecture, incorporating a pseudo floating point method of coefficient representation which affords resource efficiency for high-order designs. Furthermore, a new SRAM based delay is used to realise the decimator sample delay section. An implementation of a 2:1 decimator for 27 MHz oversampled luminance video signals using a Xilinx XC4013E FPGA is included
Keywords :
digital signal processing chips; distributed arithmetic; field programmable gate arrays; floating point arithmetic; integrated circuit design; table lookup; video signal processing; 27 MHz; FIR filter prototype; FPGA decimators; SRAM based delay; Xilinx XC4013E; coefficient representation; distributed arithmetic; high-order designs; look-up-table architecture; oversampled luminance video signals; polyphase decomposition; pseudo floating point method; resource efficiency; sample delay section; video-frequency applications; Application software; Arithmetic; Attenuation; Delay; Design engineering; Digital signal processing; Field programmable gate arrays; Finite impulse response filter; Frequency; Signal sampling;
Conference_Titel :
Electronics, Circuits and Systems, 1998 IEEE International Conference on
Conference_Location :
Lisboa
Print_ISBN :
0-7803-5008-1
DOI :
10.1109/ICECS.1998.814046
