High performance distributed arithmetic FPGA decimators for video-frequency applications

This paper describes a method of implementing high performance integer decimators for video-frequency applications using FPGAs. The decimators are derived from polyphase decomposition of an FIR filter prototype and implemented using a modified distributed arithmetic look-up-table architecture, incorporating a pseudo floating point method of coefficient representation which affords resource efficiency for high-order designs. Furthermore, a new SRAM based delay is used to realise the decimator sample delay section. An implementation of a 2:1 decimator for 27 MHz oversampled luminance video signals using a Xilinx XC4013E FPGA is included