Observable time windows: verifying the results of high-level synthesis

One of the main problems in high-level synthesis has been the lack of verification techniques for checking the equivalence between the behavioral specification and the scheduled implementation. Due to scheduling it may not be possible to compare simulation results before and after high-level synthesis using the same simulation drivers. Given that simulation is the most time consuming step in the design process, this severely reduces the advantages of high-level synthesis. This paper presents techniques and algorithms for comparing simulation results using the same simulation drivers. The approach is based on creating special hardware structures in the implementation and comparing the simulations only at synchronization points called observable time windows