DocumentCode
3441414
Title
Efficient Regular Linear Temporal Logic Using Dualization and Stratification
Author
Sanchez, Cesar ; Samborski-Forlese, Julián
Author_Institution
IMDEA Software Inst., Madrid, Spain
fYear
2012
fDate
12-14 Sept. 2012
Firstpage
13
Lastpage
20
Abstract
We study efficient translations of Regular Linear Temporal Logic (RLTL) into automata on infinite words. RLTL is a temporal logic that fuses Linear Temporal Logic (LTL) with regular expressions, extending its expressive power to all ω-regular languages. The first contribution of this paper is a novel bottom up translation from RLTL into alternating parity automata of linear size that requires only colors 0, 1 and 2. Moreover, the resulting automata enjoy the stratified internal structure of hesitant automata. Our translation is defined inductively for every operator, and does not require an upfront transformation of the expression into a normal form. Our construction builds at every step two automata: one equivalent to the formula and another to its complement. Inspired by this construction, our second contribution is to extend RLTL with new operators, including universal sequential composition, that enrich the logic with duality laws and negation normal forms. The third contribution is a ranking translation of the resulting alternating automata into non-deterministic Buuchi automata. To provide this efficient translation we introduce the notion of stratified rankings, and show how the translation is optimal for the LTL fragment of the logic.
Keywords
automata theory; duality (mathematics); formal languages; temporal logic; ω-regular languages; LTL fragment; RLTL; alternating automata ranking translation; alternating parity automata; duality laws; dualization; hesitant automata stratified internal structure; infinite words; negation normal forms; nondeterministic Buchi automata; regular expressions; regular linear temporal logic; stratification; universal sequential composition; Automata; Boolean functions; Color; Data structures; Delay; Semantics; Switches; formal methods; formal verification; temporal logic;
fLanguage
English
Publisher
ieee
Conference_Titel
Temporal Representation and Reasoning (TIME), 2012 19th International Symposium on
Conference_Location
Leicester
ISSN
1530-1311
Print_ISBN
978-1-4673-2659-9
Type
conf
DOI
10.1109/TIME.2012.25
Filename
6311110
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