Alternating strategies for sequential circuit ATPG

Author

Hsiao, Michael S. ; Rudnick, Elizabeth M. ; Patel, Janak H.

Author_Institution

Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA

fYear

1996

fDate

11-14 Mar 1996

Firstpage

368

Lastpage

374

Abstract

A new sequential circuit test generator, ALT-TEST, is described which alternates repeatedly between two phases of test generation. The first phase uses a simulation-based genetic algorithm, while the second phase uses a deterministic algorithm. The fast execution of the first phase combines with the more powerful test sequence generation and redundancy-identification capabilities of the second phase to produce test sets having high fault coverages in low execution times. The effectiveness of the approach is demonstrated on the ISCAS89 sequential benchmark circuits and several synthesized circuits

Keywords

automatic testing; deterministic algorithms; genetic algorithms; logic testing; sequential circuits; ALT-TEST; ATPG; ISCAS89; alternating strategy; automatic test pattern generation; deterministic algorithm; fault coverage; genetic algorithm; redundancy identification; sequential circuit; simulation; Automatic test pattern generation; Benchmark testing; Circuit faults; Circuit simulation; Circuit synthesis; Circuit testing; Genetic algorithms; Power generation; Sequential analysis; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1996. ED&TC 96. Proceedings

Conference_Location

Paris

ISSN

1066-1409

Print_ISBN

0-8186-7424-5

Type

conf

DOI

10.1109/EDTC.1996.494327

Filename

494327