Mechanism of moisture uptake induced via failure and its impact on 45nm node interconnect design

Author

Fujimaki, T. ; Higashi, K. ; Nakamura, N. ; Matsunaga, N. ; Yoshida, K. ; Miyawaki, N. ; Hatano, M. ; Hasunuma, M. ; Wada, J. ; Nishioka, T. ; Akiyama, K. ; Kawashima, H. ; Enomoto, Y. ; Hasegawa, T. ; Honda, K. ; Iwai, M. ; Yamada, S. ; Matsuoka, F.

Author_Institution

Semicond. Co., Toshiba Corp.

fYear

2005

fDate

5-5 Dec. 2005

Firstpage

183

Lastpage

186

Abstract

Moisture induced via failure (MIVF) is studied for 45nm interconnect technology using porous low-k films. Test patterns are designed to examine the layout dependence of the MIVF. Some fundamental and important layout dependencies of the via resistance increase are investigated and considered for the first time. It has been found that the MIVF has not been suppressed, even though multiple vias structure is adopted. On the contrary, local wiring pattern density close to via and dummy wiring pattern area size strongly affect via resistance increase. A model with moisture ventilation can successfully explain those layout dependencies. It is confirmed that the MIVF is completely suppressed by the control of dummy pattern layout

Keywords

circuit layout; cryogenic electronics; electric resistance; integrated circuit interconnections; porous materials; wiring; 45 nm; MIVF; dummy wiring pattern; layout dependence; moisture induced via failure; moisture ventilation; node interconnect design; porous low-k films; resistance increase; test patterns; wiring pattern density; CMOS process; CMOS technology; Design engineering; Large scale integration; Moisture; Plasma measurements; Research and development; Space technology; Testing; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International

Conference_Location

Washington, DC

Print_ISBN

0-7803-9268-X

Type

conf

DOI

10.1109/IEDM.2005.1609301

Filename

1609301