On test generation for interconnected finite-state machines-the output sequence justification problem

Test generation for synchronous sequential circuits can be facilitated by decomposing the circuit into a cycle free interconnection of submachines, such that all feedback loops are included within the submachines. In this work, we describe a test generation procedure that takes advantage of cycle free circuit decomposition. The paper focuses on one of the subproblems of the test generation problem, the output sequence justification problem. We propose a solution to this problem and show how it can be incorporated into a test generation procedure