System Level Delay Modeling for Network-on-Chip

To evaluate the performance of delay for Network-on-Chip (NoC) at system-level design as early as possible, a delay estimation methodology based on M/G/1 queuing theory is proposed in the paper. In this methodology, the influence of the finite buffer resources and virtual channels in NoC router on the packet latency is taken into account, and the backward algorithm is used to calculate the network average packet latency. Several experiments with different traffic loads are carried out to evaluate the efficacy of this delay model. Experimental results show that a significant improvement in evaluation speed is achieved with the proposed power model as compared with the RTL-level simulator, while maintaining a minor average error of approximately 8.0% and achieving a speedup of 250 times. As an application, the proposed model has been successfully used to evaluate the performance of different core mappings for MPEG4 decoder in system-level design.