Rapid gate matching with don´t cares

At the end of logic synthesis, the technology mapping step maps the Boolean function on physical cells. This step is based on a matching check, the complexity of which depends on the number of library cell inputs, and increases if don´t cares are considered. The method presented here is based on fault analysis. Using a structural equivalent of the cell, it allows one to prune dramatically the design space, and derives at the same time the input phase. The experimental results show a real improvement in CPU time compared to ROBDD based Boolean matching, and are promising for handling complex cells