Test and testability techniques for open defects in RAM address decoders

Author

Sachdev, Manoj

Author_Institution

Philips Res. Lab., Eindhoven, Netherlands

fYear

1996

fDate

11-14 Mar 1996

Firstpage

428

Lastpage

434

Abstract

It is a prevalent assumption that all RAM address decoder defects can be modelled as RAM array faults influencing one or more RAM cells. Therefore, can be implicitly detected by testing the RAM matrix with the march tests. Recently, we came across some failures in embedded SRAMs which were not detected by the march tests. The carried out analysis demonstrated the presence of open defects in address decoders that cannot be modelled as the conventional coupling faults, therefore, are not detected by the march tests. In this article, we present the test and testability strategies for such hard-to-detect open defects

Keywords

automatic test software; decoding; design for testability; failure analysis; fault location; integrated circuit layout; integrated circuit reliability; integrated circuit testing; integrated memory circuits; random-access storage; 6N test algorithm; DFT; RAM address decoders; RAM array faults; embedded SRAMs; march tests; open defects; test strategies; testability techniques; Circuit faults; Circuit testing; Decoding; Ear; Fault detection; Laboratories; Logic testing; Performance evaluation; Random access memory; Read-write memory;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1996. ED&TC 96. Proceedings

Conference_Location

Paris

ISSN

1066-1409

Print_ISBN

0-8186-7424-5

Type

conf

DOI

10.1109/EDTC.1996.494336

Filename

494336