Integration and optimization of embedded-sige, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies

Author

Horstmann, M. ; Wei, A. ; Kammler, Thorsten ; Hontschel, J. ; Bierstedt, H. ; Feudel, T. ; Frohberg, K. ; Gerhardt, M. ; Hellmich, A. ; Hempel, K. ; Hohage, J. ; Javorka, P. ; Klais, J. ; Koerner, G. ; Lenski, Markus ; Neu, A. ; Otterbach, R. ; Press, P.

Author_Institution

AMD Saxony LLC & Co., Dresden

fYear

2005

fDate

5-5 Dec. 2005

Firstpage

233

Lastpage

236

Abstract

An optimized 4-way stress integration on partially-depleted SOI (PD-SOI) CMOS is presented. An embedded-SiGe process and a compressive-stressed liner film are used to induce compressive strain in the PMOS (PMOS "stressors"). A stress memorization process and a tensile-stressed liner film are used to induce tensile strain in the NMOS (NMOS "stressors"). With optimization, the different stress techniques are highly compatible and additive to each other, improving PMOS and NMOS saturation drive current by 53% and 32%, respectively. This improvement results in 40% higher product speed. To demonstrate the extendibility for future transistor nodes the stress improvements were increased further resulting in record PMOS performance of IDSAT=860muA/mum at 200nA IOFF (self-heating corrected) and 1V. The stress techniques are proven in AMD\´s 90nm manufacturing processes, and have been scaled for use in 65nm manufacturing

Keywords

CMOS integrated circuits; Ge-Si alloys; MOSFET; silicon-on-insulator; stress effects; 1 V; 200 nA; 65 nm; 90 nm; NMOS saturation; NMOS stressors; PD-SOI CMOS; PMOS saturation; PMOS stressors; SOI CMOS technologies; SiGe; compressive strain; compressive stressed liner films; embedded SiGe process; partially-depleted SOI CMOS; stress memorization process; tensile strain; tensile stressed liner films; CMOS technology; Compressive stress; Etching; Germanium silicon alloys; MOS devices; Manufacturing processes; Semiconductor films; Silicon germanium; Tensile strain; Tensile stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International

Conference_Location

Washington, DC

Print_ISBN

0-7803-9268-X

Type

conf

DOI

10.1109/IEDM.2005.1609315

Filename

1609315