DocumentCode :
3441723
Title :
Record RF performance of sub-46 nm L/sub gate/ NFETs in microprocessor SOI CMOS technologies
Author :
Sungjae Lee ; Wagner, Libor ; Jagannathan, B. ; Csutak, S. ; Pekarik, Jack ; Breitwisch, M. ; Ramachandran, R. ; Freeman, G.
Author_Institution :
IBM Syst. & Technol. Group, Hopewell Junction, NY
fYear :
2005
fDate :
5-5 Dec. 2005
Firstpage :
241
Lastpage :
244
Abstract :
We report record RF FET performance in 65 and 90-nm silicon-on-insulator (SOI) CMOS technologies featuring measured gate lengths from 27 to 43 nm and analyze factors contributing to that performance. The effect of layout and geometry optimization as well as channel length scaling is investigated to improve RF performance, namely fT, and fMAX. A peak fT of 330 GHz is measured in a fully-wired 65-nm NFET. A complete de-embedding method to accurately determine RF characteristics of the intrinsic 90-nm SOI NFET results in a peak fT of 290 GHz and an fMAX of 450 GHz
Keywords :
CMOS digital integrated circuits; circuit optimisation; microprocessor chips; silicon-on-insulator; 27 to 43 nm; 330 GHz; 65 nm; 90 nm; RF FET performance; SOI NFET; channel length scaling; de-embedding method; geometry optimization; layout effect; microprocessor SOI CMOS technologies; silicon-on-insulator CMOS technologies; CMOS technology; FETs; Fingers; Immune system; Length measurement; Microprocessors; Parasitic capacitance; Radio frequency; Transconductance; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-9268-X
Type :
conf
DOI :
10.1109/IEDM.2005.1609317
Filename :
1609317
Link To Document :
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