DocumentCode
3441737
Title
An advanced low power, high performance, strained channel 65nm technology
Author
Tyagi, S. ; Auth, C. ; Bai, P. ; Curello, G. ; Deshpande, H. ; Gannavaram, S. ; Golonzka, O. ; Heussner, R. ; James, R. ; Kenyon, C. ; Lee, S.-H. ; Lindert, N. ; Liu, M. ; Nagisetty, R. ; Natarajan, S. ; Parker, C. ; Sebastian, J. ; Sell, B. ; Sivakumar,
Author_Institution
Portland Technol. Dev., Intel Corp., Hillsboro, OR
fYear
2005
fDate
5-5 Dec. 2005
Firstpage
245
Lastpage
247
Abstract
An advanced low power, strained channel, dual poly CMOS 65nm technology with enhanced transistor performance is presented. At 1V and off current of 100nA/mum, transistors have record currents of 1.21mA/mum and 0.71mA/mum for NMOS and PMOS respectively. This industry leading 65nm technology is currently in high volume manufacturing
Keywords
CMOS integrated circuits; low-power electronics; mass production; nanotechnology; 1 V; 65 nm; CMOS technology; NMOS; PMOS; enhanced transistor performance; high volume manufacturing; strained channel; Annealing; CMOS technology; Capacitive sensors; Dielectrics; Implants; MOS devices; MOSFETs; Manufacturing industries; Silicon; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
Conference_Location
Washington, DC
Print_ISBN
0-7803-9268-X
Type
conf
DOI
10.1109/IEDM.2005.1609318
Filename
1609318
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