• DocumentCode
    3441901
  • Title

    Parallel decomposition of multipliers modulo (2n±1)

  • Author

    Skavantzos, Alexander ; Taylor, Fred J.

  • Author_Institution
    Dept. of Electr. Eng., Louisiana State Univ., Baton Rouge, LA, USA
  • fYear
    1988
  • fDate
    3-5 Oct 1988
  • Firstpage
    502
  • Lastpage
    506
  • Abstract
    The authors discuss the mathematical basis and hardware implementations of large-word length multipliers (mod 2n±1). The focus is on a recently developed parallel arithmetic system named the polynomial residue-number system (see A. Skavantzos, 1987). The proposed multipliers allow a variety of implementation options and are shown to have much better performance than multipliers based on traditional techniques. The performance improvement is most obvious in multiplication-intensive environments
  • Keywords
    digital arithmetic; multiplying circuits; parallel algorithms; parallel architectures; hardware implementations; large-word length multipliers; multiplication-intensive environments; multiplier decomposition; parallel arithmetic system; parallel decomposition; polynomial residue-number system; Arithmetic; Autocorrelation; Convolution; Discrete Fourier transforms; Ducts; Fast Fourier transforms; Hardware; Niobium; Polynomials; Signal processing algorithms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on
  • Conference_Location
    Rye Brook, NY
  • Print_ISBN
    0-8186-0872-2
  • Type

    conf

  • DOI
    10.1109/ICCD.1988.25751
  • Filename
    25751
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3441901