Efficient fast transform processor with cost-effective hardware sharing architecture for multi-standard video encoding

In this paper, fast multiple forward transform algorithms and their hardware sharing designs for 2×2, 4×4, and 8×8 forward transforms in H.264/AVC, and the 8×8 forward transform in AVS, 4×4 and 8×8 forward transforms in VC-1, and DCT in JPEG, MPEG-1/2/4 are developed with a cost effective hardware for the multi-standard video encoding applications. By only shift-and-addition computations, the proposed 1-D hardware sharing transform scheme requires 16.5K gates and is achieved without multiplications. The proposed 1-D sharing architecture reduces the numbers of shifters and adders by up to 36% and 49% respectively, compared with the individual and separate fast algorithm schemes. By VLSI implementations, the 2-D transform processor with the proposed 1-D sharing architecture achieves multi-standard real-time 1080HD video encoding.