Design for testability of gated-clock FSMs

Gated clocks allow significant power savings in synchronous systems, but are generally considered an unsafe design practice because they decrease testability. In this paper we present two methodologies that guarantee full single-stuck-at testability for gated-clock finite-state machines. The first technique, increased observability, can be used in conjunction with redundancy-removal techniques to obtain fully-testable gated clock FSMs with high performance. The second technique, increased observability and controllability, is applicable to large FSMs for which redundancy removal is not possible and produces fully-testable gated-clock FSMs with a moderate decrease in performance