A novel capacitor-less DRAM cell using thin capacitively-coupled thyristor (TCCT)

Author

Cho, Hyun-Jin ; Nemati, Farid ; Roy, Rich ; Gupta, Rajesh ; Yang, Kevin ; Ershov, Maxim ; Banna, Srinivasa ; Tarabbia, Marc ; Sailing, C. ; Hayes, Dennis ; Mittal, Anurag ; Robins, Scott

Author_Institution

T-RAM Semicond., San Jose, CA

fYear

2005

fDate

5-5 Dec. 2005

Firstpage

311

Lastpage

314

Abstract

A capacitor-less DRAM cell using a thin capacitively-coupled thyristor (TCCT DRAM) is introduced. Experimental results from unit memory cell fabricated in a 130nm SOI logic technology demonstrate Ion/Ioff ratio of 10⁷, non-destructive read; write speed less than 2ns at 125C, and solid retention characteristics. These cell characteristics combined with a small cell area (as low as 9F²) and simple process integration make TCCT DRAM a suitable candidate for high-performance high-density embedded or standalone memory applications

Keywords

DRAM chips; silicon-on-insulator; thyristors; 125 C; 130 nm; SOI logic technology; capacitorless DRAM cell; cell characteristics; embedded memory; nondestructive read; process integration; solid retention characteristics; standalone memory; thin capacitively-coupled thyristor; Anodes; CMOS technology; Cathodes; Logic; MOSFET circuits; Manufacturing; Random access memory; Read-write memory; Solids; Thyristors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International

Conference_Location

Washington, DC

Print_ISBN

0-7803-9268-X

Type

conf

DOI

10.1109/IEDM.2005.1609337

Filename

1609337