FPGA synthesis for minimum area, delay and power

Author

Pan, K.-R.R. ; Pedram, Massoud

Author_Institution

Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA

fYear

1996

fDate

11-14 Mar 1996

Firstpage

603

Abstract

In this paper, we address the problems of minimizing the area, delay and power during synthesis of field programmable gate arrays (FPGAs). We use Boolean decomposition techniques to minimize the number of configurable logic blocks (CLBs), the depth of the network and the power dissipations. We use OBDDs to represent functions so that our methods can be implemented more effectively. Our mapping algorithm is based on function decomposition which was pioneered by Ashenhurst [1959]

Keywords

Boolean functions; field programmable gate arrays; logic CAD; Boolean decomposition techniques; FPGA synthesis; OBDDs; area; configurable logic blocks; delay; field programmable gate arrays; function decomposition; mapping algorithm; power; power dissipations; Circuits; Contracts; Costs; Delay; Energy consumption; Field programmable gate arrays; Minimization methods; Network synthesis; Programmable logic arrays; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1996. ED&TC 96. Proceedings

Conference_Location

Paris

ISSN

1066-1409

Print_ISBN

0-8186-7424-5

Type

conf

DOI

10.1109/EDTC.1996.494367

Filename

494367

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3442166