Title :
Search of optimal solutions in multi-level neural networks
Author :
Bang, Sa Hyun ; Sheu, Bing J. ; Chang, Josephine C F
Author_Institution :
Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
fDate :
30 May-2 Jun 1994
Abstract :
The output of a multi-level neuron produces a multibit representation. The total network size with multilevel neurons can therefore be significantly reduced from a conventional network with two-level neurons. The reduction in network size benefits VLSI implementation. Due to the nonlinearity associated with a neuron transfer function, multiple local minima exist in the energy function of a multi-level analog-to-digital decision network. The procedure for applying hardware annealing by continuously changing the neuron gain from a low value to a certain high value, to reach the globally optimal solution is described. Several simulation results are also presented. The parallel hardware annealing method is much faster than the simulated annealing method on digital computers
Keywords :
Hopfield neural nets; VLSI; circuit analysis computing; circuit optimisation; neural chips; transfer functions; VLSI implementation; analog-to-digital decision network; globally optimal solution; hardware annealing; multi-level neural networks; multiple local minima; network size; neuron gain; neuron transfer function; simulation results; Computational modeling; Hardware; Intelligent networks; Neural networks; Neurons; Optimization methods; Silicon; Simulated annealing; Very large scale integration; Voltage;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.409616
