Highly scalable flash memory with novel deep trench isolation embedded into highperformance cmos for the 90nm node & beyond

Author

Shum, D. ; Tilke, A.T. ; Pescini, L. ; Stiftinger, M. ; Kakoschke, R. ; Han, K.J. ; Kim, S.R. ; Hecht, V. ; Chan, N. ; Yang, A. ; Broze, R.

Author_Institution

Infineon Technol. NA, Hopewell Junction, NY

fYear

2005

fDate

5-5 Dec. 2005

Firstpage

344

Lastpage

347

Abstract

A flash memory cell with 90nm ground-rules has been embedded in a high performance (HP) CMOS logic process. A deep trench isolation (DTi) process module enables an isolated Pwell (IPW) bias scheme for the first time, leading to flash write/erase (W/E) by FN tunneling without GIDL, a key feature for low-power (LP) electronics. IPW leads to a compact cell design and a highly scalable high-voltage (HV) periphery through the narrow intrawell and interwell isolation spaces. The memory arrays are defined by DTi of each bitline (BL) from its neighboring BL. The HV bias can be scaled with a carefully designed retrograde triple-well that enables a symmetrical gate-well bias

Keywords

CMOS memory circuits; flash memories; isolation technology; low-power electronics; 90 nm; CMOS logic process; deep trench isolation; flash memory; high-voltage periphery; interwell isolation spaces; isolated Pwell bias scheme; low-power electronics; memory arrays; symmetrical gate-well bias; CMOS logic circuits; CMOS process; CMOS technology; Etching; Flash memory; Flash memory cells; Isolation technology; Log periodic antennas; Logic arrays; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International

Conference_Location

Washington, DC

Print_ISBN

0-7803-9268-X

Type

conf

DOI

10.1109/IEDM.2005.1609346

Filename

1609346