DocumentCode
3442269
Title
New three-dimensional integration technology using self-assembly technique
Author
Fukushima, Takafumi ; Yamada, Yusuke ; Kikuchi, Hirokazu ; Koyanagi, Mitsumasa
Author_Institution
Dept. of Bioeng. & Robotics, Tohoku Univ., Sendai
fYear
2005
fDate
5-5 Dec. 2005
Firstpage
348
Lastpage
351
Abstract
To achieve ultimate super chip integration, we have developed a three-dimensional integration technology called super-smart-stack technology using a self-assembly technique. The chip alignment accuracy of within 1mum is obtained by the self-assembly technique. We demonstrated for the first time that 3D SRAM test chip with ten memory layers was successfully fabricated using the super-smart-stack (SSS) technology
Keywords
SRAM chips; self-assembly; 3D SRAM; 3D integration; self-assembly; super chip integration; super-smart-stack technology; Biomedical engineering; Dielectric substrates; Energy consumption; Fabrication; Large scale integration; Robotic assembly; Robots; Self-assembly; Stacking; Wafer bonding;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
Conference_Location
Washington, DC
Print_ISBN
0-7803-9268-X
Type
conf
DOI
10.1109/IEDM.2005.1609347
Filename
1609347
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