Enabling SOI-based assembly technology for three-dimensional (3d) integrated circuits (ICs)

Author

Topol, A.W. ; La Tulipe, D.C. ; Shi, L. ; Alam, S.M. ; Frank, D.J. ; Steen, S.E. ; Vichiconti, J. ; Posillico, D. ; Cobb, M. ; Medd, S. ; Patel, J. ; Goma, S. ; Dimilia, D. ; Robson, M.T. ; Duch, E. ; Farinelli, M. ; Wang, C. ; Conti, R.A. ; Canaperi, D.M

Author_Institution

IBM T. J. Watson Res. Center, Yorktown Heights, NY

fYear

2005

fDate

5-5 Dec. 2005

Firstpage

352

Lastpage

355

Abstract

We present solutions to the key process technology challenges of three-dimensional (3D) integrated circuits (ICs) that enable creation of stacked device layers with the shortest distance between them, the highest interconnection density and extremely aggressive wafer-to-wafer alignment. To achieve this important 3D IC technology milestone, we optimized the layer transfer process to include a glass handle wafer, oxide fusion bonding, wafer bow compensation methods, and a single damascene patterning and metallization method for creation of high-aspect-ratio (6:1 < AR < 11:1) contacts between two stacked device layers

Keywords

assembling; integrated circuit interconnections; integrated circuit metallisation; silicon-on-insulator; wafer bonding; 3D integrated circuits; assembly technology; glass handle wafer; high-aspect-ratio contacts; layer transfer process; metallization method; oxide fusion bonding; silicon-on-insulator; single damascene patterning; stacked device layers; wafer bow compensation; Assembly; CMOS technology; Fabrication; Glass; Integrated circuit interconnections; Integrated circuit technology; Joining processes; Optimization methods; Three-dimensional integrated circuits; Wafer bonding;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International

Conference_Location

Washington, DC

Print_ISBN

0-7803-9268-X

Type

conf

DOI

10.1109/IEDM.2005.1609348

Filename

1609348