DocumentCode
3442333
Title
Hardware check of arithmetic devices with abridged execution of operations
Author
Drozd, A. ; Lobachov, M. ; Hassonah, W.
Author_Institution
Dept. of Comput., Odessa State Polytech. Univ., Ukraine
fYear
1996
fDate
11-14 Mar 1996
Firstpage
611
Abstract
The authors propose the checking by a module method of the multiplier in a high-performance floating-point arithmetic device. This process of checking defines the common approach to the modular checking of arithmetic devices with abridged execution of operations. The process consists of a checking code of the rounded result formed by the checking codes of the operands and its parts
Keywords
digital arithmetic; error detection codes; floating point arithmetic; logic testing; multiplying circuits; abridged execution of operations; checking code; floating-point arithmetic device; hardware check; modular checking; module method; multiplier; Circuits; Floating-point arithmetic; Hardware; Indexing; Production; Testing; Zinc;
fLanguage
English
Publisher
ieee
Conference_Titel
European Design and Test Conference, 1996. ED&TC 96. Proceedings
Conference_Location
Paris
ISSN
1066-1409
Print_ISBN
0-8186-7424-5
Type
conf
DOI
10.1109/EDTC.1996.494375
Filename
494375
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