High performance gate first HfSiON dielectric satisfying 45nm node requirements

Author

Quevedo-Lopez, M.A. ; Krishnan, S.A. ; Kirsch, P.D. ; Li, H.J. ; Sim, J.H. ; Huffman, C. ; Peterson, J.J. ; Lee, B.H. ; Pant, G. ; Gnade, B.E ; Kim, M.J. ; Wallace, R.M. ; Guo, D. ; Bu, H. ; Ma, T.P.

Author_Institution

Texas Instrum., Austin, TX

fYear

2005

fDate

5-5 Dec. 2005

Lastpage

428

Abstract

We show an ALD based HfSiON gate dielectric scaled to 1 nm EOT with excellent performance and reliability. Furthermore, the HfSiON dielectric films are integrated in a gate first approach that includes a 1000degC-5s anneal. It is also demonstrated that this 1 nm EOT HfSiON can achieve electron and hole mobilities comparable to that of SiON. This progress is enabled due to better understanding of the relationship between charge trapping, HfSiON thickness and crystallinity. Performance and reliability improvement is attributed to reduced charge trapping due to suppressed crystallization of the optimized HfSiON films

Keywords

atomic layer deposition; dielectric thin films; electron mobility; hafnium compounds; hole mobility; interface states; reliability; silicon compounds; 1 nm; 1000 C; 45 nm; 5 s; ALD based gate dielectric; HfSiON; annealing processing; charge trapping; crystallization; dielectric films; electron mobility; hole mobility; Annealing; Crystallization; Dielectrics; Electrodes; Electron traps; Instruments; Leakage current; MOS devices; Microelectronics; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International

Conference_Location

Washington, DC

Print_ISBN

0-7803-9268-X

Type

conf

DOI

10.1109/IEDM.2005.1609369

Filename

1609369