Level-converter aware supply voltage scaling for reducing dynamic power dissipation in clocked sequential designs

In this paper, we propose a mixed integer linear program (MILP) to solve the problem of optimal unification of low-supply-voltage assignment and retiming to reduce dynamic power dissipation under timing constrains for the case of clocked sequential digital designs. We address this problem at the system level where computational elements are multipliers and adders for instance. Assuming flip-flops are able to provide level-conversion from low to high supply voltage when this is needed, the proposed MILP optimally solves this problem without inserting level converters on wires that do not have registers on them. Experimental results have shown that this MILP can produce designs with reduced dynamic power dissipation.