A system for asynchronous high-speed chip to chip communication

Author

Roine, Per Torstein

Author_Institution

Dept. of Inf., Oslo Univ., Norway

fYear

1996

fDate

18-21 Mar 1996

Firstpage

2

Lastpage

10

Abstract

A system for high-speed asynchronous interconnections between VLSI chips is proposed. Communication is performed on three-wire links that have about the same properties as differential interconnections. A bit transmission consists of switching the constant driver current from one wire to one of the two others. There is no need for clocking or synchronisation, as bits are separated by a transition. The chosen data representation makes decoding to a two-phase protocol especially simple. Energy consumption may be reduced by dynamically adjusting bias currents, and thus circuit speed, to match the demand for communication bandwidth. In a 0.7 μm CMOS process, communication bandwidth per link is expected to reach 1 Gb/s

Keywords

VLSI; data communication; integrated circuit interconnections; logic design; VLSI chips; asynchronous interconnections; bit transmission; chip to chip communication; constant driver current; data representation; three-wire links; Bandwidth; Clocks; Communication switching; Decoding; Driver circuits; Integrated circuit interconnections; Protocols; Synchronization; Very large scale integration; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Research in Asynchronous Circuits and Systems, 1996. Proceedings., Second International Symposium on

Conference_Location

Fukushima

Print_ISBN

0-8186-7298-6

Type

conf

DOI

10.1109/ASYNC.1996.494432

Filename

494432