Stress memorization in high-performance FDSOI devices with ultra-thin silicon channels and 25nm gate lengths

Author

Singh, D.V. ; Sleight, J.W. ; Hergenrother, J.M. ; Ren, Z. ; Jenkins, K.A. ; Dokumaci, O. ; Black, L. ; Chang, J.B. ; Nakayama, H. ; Chidambarrao, D. ; Venigalla, R. ; Pan, J. ; Natzle, W. ; Tessier, B.L. ; Nomura, A. ; Ott, J.A. ; Ieong, M. ; Haensch, W.

Author_Institution

T. J. Watson Res. Center, IBM Semicond. R&D Center, Yorktown Heights, NY

fYear

2005

fDate

5-5 Dec. 2005

Firstpage

505

Lastpage

508

Abstract

We report for the first time, the effect of stress memorization (SM), and the combined effects of SM and dual stress liner (DSL) on high performance fully-depleted ultra-thin channel devices with a raised source/drain architecture and channel thickness of 18nm. SM results in significant drive current and mobility enhancement, comparable to that obtained using the DSL approach. Stress transfer to the channel during SM likely occurs through the poly-gate, becoming more effective as the body is thinned. Combining SM and DSL results in a net gain that is substantially larger than that obtained using each technique separately

Keywords

carrier mobility; field effect devices; silicon-on-insulator; stress effects; 18 nm; 25 nm; FDSOI devices; dual stress liner; mobility enhancement; raised source-drain architecture; stress memorization; ultra-thin silicon channel; Capacitance; DSL; Degradation; Implants; MOSFETs; Research and development; Samarium; Silicides; Silicon; Tensile stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International

Conference_Location

Washington, DC

Print_ISBN

0-7803-9268-X

Type

conf

DOI

10.1109/IEDM.2005.1609392

Filename

1609392