DocumentCode
3443195
Title
General conditions for the decomposition of state holding elements
Author
Burns, Steven M.
Author_Institution
Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
fYear
1996
fDate
18-21 Mar 1996
Firstpage
48
Lastpage
57
Abstract
A fundamental problem in the design of speed-independent asynchronous circuits is the decomposition or splitting up of high-fanin operators into two or more lower-fanin operators. In this paper, we develop general techniques to decided whether a particular decomposition of an arbitrary state-holding or combinational element into two elements with an belated internal signal is correct. These techniques are extended to determine efficiently all legal decompositions in a parameterized family
Keywords
asynchronous circuits; combinational circuits; logic design; asynchronous circuits; belated internal signal; combinational element; decomposition; legal decompositions; state holding elements; Asynchronous circuits; Circuit synthesis; Computer science; Design engineering; Fires; Law; Legal factors; Production; Sufficient conditions; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Research in Asynchronous Circuits and Systems, 1996. Proceedings., Second International Symposium on
Conference_Location
Fukushima
Print_ISBN
0-8186-7298-6
Type
conf
DOI
10.1109/ASYNC.1996.494437
Filename
494437
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