Static scheduling of instructions on micronet-based asynchronous processors

Author

Arvind, D.K. ; Rebello, V. E F

Author_Institution

Dept. of Comput. Sci., Edinburgh Univ., UK

fYear

1996

fDate

18-21 Mar 1996

Firstpage

80

Lastpage

91

Abstract

This paper investigates issues which impinge on the design of static instruction schedulers for micronet-based asynchronous processor (MAP) architectures. The micronet model exposes both temporal and spatial concurrency within a processor. A list scheduling algorithm is described which has been optimised with MAP-specific heuristics. Their performance on some program graphs are presented and conclusions are drawn on the suitability of MAP as targets for ILP compilers

Keywords

parallel architectures; processor scheduling; scheduling; Asynchronous Processor Architecture; Instruction-level Parallelism; MAP-specific heuristics; asynchronous processors; list scheduling algorithm; micronet mode; micronets; program graphs; static instruction schedulers; static scheduling; Computer science; Concurrent computing; Delay; Hardware; Pipelines; Process design; Processor scheduling; Program processors; Reduced instruction set computing; Scheduling algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Research in Asynchronous Circuits and Systems, 1996. Proceedings., Second International Symposium on

Conference_Location

Fukushima

Print_ISBN

0-8186-7298-6

Type

conf

DOI

10.1109/ASYNC.1996.494440

Filename

494440