APES: an integrated system for behavioral design, simulation and evaluation of array processors

Author

Distante, F.

Author_Institution

Dept. of Electron., Politecnico di Milano

fYear

1988

fDate

3-5 Oct 1988

Firstpage

568

Lastpage

572

Abstract

The APES system for the design and evaluation of VLSI or WSI array processors is presented. APES makes it possible to study fault-tolerant array architectures and methodologies by simulating the behavior of the system when faults occur: the type and distribution of faults can be defined by the designer. A diagnostic tool is integrated in APES to evaluate the fault-detection and error-correction capabilities of the system under observation. Another tool makes it possible to perform and evaluate the array reconfiguration after fault occurrence by adopting a user-defined strategy. Features including data entry (using a graphic editor or a hardware description language), the simulation engine, the fault injector, the diagnostic evaluator, and the restructuring/reconfiguration manager are discussed

Keywords

VLSI; fault tolerant computing; APES; VLSI; WSI; array processors evaluation; behavioral design; diagnostic evaluator; diagnostic tool; error-correction capabilities; fault injector; fault-detection; graphic editor; hardware description language; integrated system; restructuring/reconfiguration manager; simulation; simulation engine; user-defined strategy; Algorithm design and analysis; Computational modeling; Design automation; Fault tolerance; Fault tolerant systems; Graphics; Logic arrays; Performance evaluation; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on

Conference_Location

Rye Brook, NY

Print_ISBN

0-8186-0872-2

Type

conf

DOI

10.1109/ICCD.1988.25764

Filename

25764