Title :
4-bit per cell NROM reliability
Author :
Eitan, Boaz ; Cohen, Guy ; Shappir, Assaf ; Lusky, Eli ; Givant, Amichai ; Janai, Meir ; Bloom, Ilan ; Polansky, Yan ; Dadashev, Oleg ; Lavan, Avi ; Sahar, Ran ; Maayan, Eduardo
Author_Institution :
Saifun Semicond. Ltd., Netanya
Abstract :
The realization of a 4-bit NROM cell is possible due to the two physically separated bits on each side of the cell. Only 4 Vt levels on each bit are required. Key features of a 4-bit product are optimized technology, accurate and fast programming algorithm (3MB/s write speed), no single bit failures and window sensing with moving reference as an error detection and correction scheme
Keywords :
circuit reliability; random-access storage; read-only storage; 3 Mbit/s; 4 bit; NROM cell; NROM reliability; error correction scheme; error detection scheme; fast programming algorithm; Costs; Dielectrics; Error correction; Hot carriers; Nonvolatile memory; Radio access networks; Threshold voltage; Tunneling;
Conference_Titel :
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-9268-X
DOI :
10.1109/IEDM.2005.1609402
