Title :
High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability
Author :
Suk, Sung Dae ; Lee, Sung-Young ; Kim, Sung-Min ; Yoon, Eun-Jung ; Kim, Min-Sang ; Li, Ming ; Oh, Chang Woo ; Yeo, Kyoung Hwan ; Kim, Sung Hwan ; Shin, Dong-Suk ; Lee, Kwan-Heum ; Heung Sik Park ; Han, Jeong Nam ; Park, Donggun ; Jong-Bong Park ; Kim, Don
Author_Institution :
Device Res. Team, Samsung Electron. Co., Gyeonggi-Do
Abstract :
For the first time, we have successfully fabricated gate-all-around twin silicon nanowire transistor (TSNWFET) on bulk Si wafer using self-aligned damascene-gate process. With 10nm diameter nanowire, saturation currents through twin nanowires of 2.64 mA/mum, 1.11 mA/mum for n-channel TSNWFET and p-channel TSNWFET are obtained, respectively. No roll-off of threshold voltages, ~70 mV/dec. of substhreshold swing (SS), and ~20 mV/V of drain induced barrier lowering(DIBL) down to 30 nm gate length are observed for both n-ch and p-ch TSNWFETs
Keywords :
MOSFET; elemental semiconductors; nanowires; semiconductor device reliability; silicon; 10 nm; 5 nm; Si; damascene-gate process; drain induced barrier lowering; saturation currents; threshold voltage roll-off; twin silicon nanowire MOSFET; Annealing; CMOS process; Etching; Fabrication; Germanium silicon alloys; MOSFET circuits; Nanoscale devices; Research and development; Silicon compounds; Silicon germanium;
Conference_Titel :
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-9268-X
DOI :
10.1109/IEDM.2005.1609453
