Integration of a double polysilicon, fully self-aligned bipolar transistor into a 0.5 μm BiCMOS technology for fast 4 MBit SRAMs

Author

Hayden, J.D. ; Burnett, J.D. ; Perera, A.H. ; Mele, T.C. ; Walczyk, F.W. ; Kaushik, V. ; Lage, C.S. ; See, Y.C.

Author_Institution

Motorola Inc., Austin, TX, USA

fYear

1991

fDate

9-10 Sep 1991

Firstpage

17

Lastpage

20

Abstract

The single polysilicon, non-self-aligned bipolar transistor in a 0.5-μm BiCMOS technology has been converted to a double polysilicon, fully self-aligned bipolar device with little increase in process complexity. Improved bipolar performance in the form of smaller base resistance, larger knee current, higher peak cutoff frequency, and shorter ECL gate delay has been demonstrated. This technology will prove useful in meeting the requirements for higher performance in fast, high-density SRAM circuits

Keywords

BIMOS integrated circuits; SRAM chips; bipolar transistors; integrated circuit technology; 0.5 micron; 4 Mbit; BiCMOS technology; ECL gate delay; Si; base resistance; double polysilicon; fully self-aligned bipolar transistor; high-density SRAM circuits; knee current; peak cutoff frequency; submicron IC; BiCMOS integrated circuits; Bipolar transistors; Capacitance; Delay; Implants; Isolation technology; MOSFET circuits; Random access memory; Silicon; Tellurium;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar Circuits and Technology Meeting, 1991., Proceedings of the 1991

Conference_Location

Minneapolis, MN

Print_ISBN

0-7803-0103-X

Type

conf

DOI

10.1109/BIPOL.1991.160947

Filename

160947