The bit error probability performance for a digital PLL based MPSK demodulator

The authors present a statistical characterization of a uniformly sampled, first-order, decision-directed (DD), digitally implemented phase-locked loop (DPLL) for MPSK modulations. The phase detector (PD) considered has an ideal sawtooth form. A discrete-time Markov chain characterizes the DPLL and the associated PD. The signal, demodulator, and loop models are presented. The Markov chain describing the DD-DPLL operation is developed. Numerical considerations are discussed, and the steady-state phase error density functions are derived. These results are used to calculate the bit error probability for BPSK, QPSK, and 8PSK DPLL-based demodulators