Author :
Liu, Y.C. ; Pan, J.W. ; Chang, T.Y. ; Liu, P.W. ; Lan, B.C. ; Tung, C.H. ; Tsai, C.H. ; Chen, T.F. ; Lee, C.J. ; Wang, W.M. ; Chen, Y.A. ; Shih, H.L. ; Tung, L.Y. ; Cheng, L.W. ; Shen, T.M. ; Chiang, S.C. ; Lu, M.F. ; Chang, W.T. ; Luo, Y.H. ; Nayak, D. ;
Abstract :
For the first time, 75% and 7% drive current improvement is simultaneously achieved in both N/PMOS by adopting ultimate spacer process (USP) with a single stress liner. High out-of-plane stress in the channel accounts for the simultaneously enhanced drive current in N/PMOS. A 15% speed enhancement without compromising yield and product qualification in field-programmable gate arrays (FPGA) confirms immediate manufacturing feasibility of USP. This process provides a unique approach to significantly enhance device performance for 65nm CMOS technology and beyond. Extreme current increase of 25% in NMOS and 35% in PMOS can be achieved by applying additional strain enhancement methods
Keywords :
MOSFET; carrier mobility; field programmable gate arrays; semiconductor technology; 65 nm; CMOS technology; FPGA; NMOS; PMOS; USP; current enhancement; drive current improvement; field-programmable gate arrays; out-of-plane stress; strain enhancement method; stress liner; ultimate spacer process; CMOS process; CMOS technology; Capacitive sensors; Field programmable gate arrays; MOS devices; Microelectronics; Performance gain; Qualifications; Space technology; Tensile stress;
