Title :
Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm finfet with elevated source/drain extension
Author :
Kaneko, A. ; Yagishita, A. ; Yahashi, K. ; Kubota, T. ; Omura, M. ; Matsuo, K. ; Mizushima, I. ; Okano, K. ; Kawasaki, H. ; Inaba, S. ; Izumida, T. ; Kanemura, T. ; Aoki, N. ; Ishimaru, K. ; Ishiuchi, H. ; Suguro, K. ; Eguchi, K. ; Tsunashima, Y.
Author_Institution :
Process & Manuf. Eng. Center, Toshiba Corp. Semicond. Co., Yokohama
Abstract :
We present the FinFET process integration technology including improved sidewall transfer (SWT) process applicable to both fins and gates. Using this process, the uniform electrical characteristics of the ultra-small FinFETs of 15nm gate length and 10 nm fin width have been demonstrated. A new process technique for the selective gate sidewall spacer formation (spacer formation only on the gate sidewall, no spacer on the fin sidewall) is also demonstrated for realizing low-resistance elevated source/drain (S/D) extension
Keywords :
MOSFET; nanotechnology; 10 nm; 15 nm; FinFET; elevated source/drain extension; process integration technology; selective gate sidewall spacer formation; sidewall transfer process; uniform electrical characteristic; Electric variables; Epitaxial growth; Fabrication; FinFETs; Manufacturing processes; Planarization; Semiconductor device manufacture; Semiconductor films; Silicon compounds; Space technology;
Conference_Titel :
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-9268-X
DOI :
10.1109/IEDM.2005.1609488
