DocumentCode :
3445293
Title :
A 65nm NOR flash technology with 0.042/spl mu/m/sup 2/ cell size for high performance multilevel application
Author :
Servalli, G. ; Brazzelli, D. ; Camerlenghi, E. ; Capetti, G. ; Costantini, S. ; Cupeta, C. ; DeSimone, D. ; Ghetti, A. ; Ghilardi, T. ; Gulli, P. ; Mariani, M. ; Pavan, A. ; Somaschini, R.
Author_Institution :
FTM-Adv. R&D, STMicroelectronics, Milan
fYear :
2005
fDate :
5-5 Dec. 2005
Firstpage :
849
Lastpage :
852
Abstract :
A 65nm NOR flash technology, featuring a true 10lambda2 , 0.042mum2 cell, is presented for the first time for 1bit/cell and 2bit/cell products. Advanced 193nm lithography, floating gate self aligned STI, cobalt salicide and three levels of copper metallization allow the integration with a high density and high performance 1.8V CMOS
Keywords :
CMOS logic circuits; NOR circuits; flash memories; lithography; metallisation; 1.8 V; 65 nm; NOR flash technology; cobalt salicide; copper metallization; floating gate self aligned STI; lithography; multilevel application; Bismuth; Cobalt; Copper; Decoding; Dielectrics; Isolation technology; Lithography; Nonvolatile memory; Optical arrays; Space technology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-9268-X
Type :
conf
DOI :
10.1109/IEDM.2005.1609490
Filename :
1609490
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3445293
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