Experimental and theoretical analysis of scaling issues in dual-bit discrete trap non-volatile memories

Here we present an experimental and theoretical analysis of dual-bit DT-NVMs. In particular data retention experiments on bulk and SOI silicon nanocrystal memory devices and their interpretation through a surface potential based model are shown (Perniola et al., 2005). Our model is then exploited to investigate the main issues posed by dual-bit reading, when the dimensions of bulk and SOI devices are scaled down. We present two different reading schemes for a scaled device and we show that dual-bit performance of DT-NVMs, charged on both sides, is preserved even when the two pockets of charge coalesce. Finally, we conclude that both bulk and SOI dual-bit architectures are promising for memory cells with gate lengths down to 30-50 nm