Title :
The Shuffle-Exchange Mesh Topology for 3D NoCs
Author :
Sharifi, Akbar ; Sabbaghi-Nadooshan, Reza ; Sarbazi-Azad, Hamid
Author_Institution :
Sharif Univ. of Technol., Tehran
Abstract :
Nowadays networks-on-chip are emerging as a hot topic in IC designs with high integration. In addition to popular mesh and torus topologies, other structures can also be considered especially in 3D VLSI design. The shuffle-exchange topology is one of the popular interconnection architectures for multiprocessors due to its scalability and self-routing capability. By vertically stacking two or more silicon wafers, connected with a high-density and high-speed interconnect, it is now possible to combine multiple active device layers within a single IC. In this paper we propose an efficient three dimensional layout for a novel 2D mesh structure based on the shuffle-exchange topology. Simulation results show that by using the third dimension, performance and latency can be improved compared to the 2D VLSI implementation.
Keywords :
VLSI; integrated circuit design; integrated circuit layout; multiprocessor interconnection networks; network topology; network-on-chip; 3D NoC; 3D VLSI design; IC design; interconnection architecture; networks-on-chip; shuffle-exchange mesh topology; three dimensional layout; Circuit topology; Computer science; Costs; Delay; Integrated circuit interconnections; Network topology; Network-on-a-chip; Parallel architectures; Routing; Very large scale integration; 3D NoCs; 3D VLSI; Performance evaluation; Power consumption; Shuffle-Exchange.; SoC;
Conference_Titel :
Parallel Architectures, Algorithms, and Networks, 2008. I-SPAN 2008. International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
978-0-7695-3125-0
DOI :
10.1109/I-SPAN.2008.23
