Title :
A RISC architecture to explore HW/SW parallelism in HW/SW codesign
Author :
Carro, Luigi ; Suzim, A.
Author_Institution :
Departamento de Engenharia Eletrica, Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil
Abstract :
The paper describes some modifications on the architecture of embedded RISC-like processors to better explore HW/SW (hardware/software) parallelism in a HW/SW co-design environment. It is shown that the inclusion of an instruction memory allows parallel execution of the application SW and eventual dedicated HW. Positive results are shown for two different RISC microprocessors. The paper also reports experimental results, particularly the proposed modifications applied to an induction motor control algorithm
Keywords :
CAD; computer aided software engineering; concurrent engineering; development systems; induction motors; machine control; microprocessor chips; reduced instruction set computing; RISC architecture; RISC microprocessors; embedded RISC-like processors; hardware/software codesign; hardware/software parallelism; induction motor control algorithm; instruction memory; parallel execution; CMOS technology; Computer architecture; Concurrent computing; Control systems; Costs; Embedded computing; Induction motors; Microprocessors; Parallel processing; Reduced instruction set computing;
Conference_Titel :
Engineering of Computer-Based Systems,1996. Proceedings., IEEE Symposium and Workshop on
Conference_Location :
Friedrichshafen
Print_ISBN :
0-8186-7355-9
DOI :
10.1109/ECBS.1996.494564
