Title :
0.1/spl mu/m poly-Si thin film transistors for system-on-panel (SoP) applications
Author :
Tsui, Bing-Yue ; Lin, Chia-Pin ; Huang, Chih-Feng ; Xiao, Yi-Hsuan
Abstract :
Thin active layer, fully-silicided source/drain (S/D), modified Schottky barrier, high dielectric constant (high-k) gate dielectric, and metal gate technologies are integrated to realize high performance TFTs. Devices with 0.1 mum channel length were fabricated successfully. Low threshold voltage, low subthreshold swing, high effective mobility, low S/D resistance, high on/off current ratio, and good control of threshold voltage are demonstrated
Keywords :
Schottky barriers; high-k dielectric thin films; thin film transistors; 1 micron; Schottky barrier; dielectric constant; high-k gate dielectric; metal gate technologies; subthreshold swing; system-on-panel; thin film transistors; threshold voltage; Crystallization; Dielectric constant; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; Plasma temperature; Rapid thermal annealing; Schottky barriers; Thin film transistors; Threshold voltage;
Conference_Titel :
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-9268-X
DOI :
10.1109/IEDM.2005.1609507
