Title :
Low temperature single grain thin film transistor (LTSG-TFT) with SOI performance using cmp-flattened /spl mu/-czochralski process
Author :
Shimada, Hiroyuki ; Hiroshima, Yasushi ; Shimoda, Tatsuya
Author_Institution :
Technol. Platform Res. Center, Seiko Epson Corp., Nagano
Abstract :
We succeeded in fabricating low temperature single grain thin film transistor (LTSG-TFT) devices with excellent characteristics by using the CMP-flattened mu-Czochralski process for 3D integrated circuits application. The LTSG-TFT devices demonstrated high drivability comparable to that of SOI-MOSFETs and an excellent gate delay time of 65psec was obtained despite the use of fully low temperature processing
Keywords :
MOSFET; chemical mechanical polishing; crystal growth from melt; silicon-on-insulator; thin film transistors; 3D integrated circuits; SOI-MOSFET; chemical mechanical polishing; mu-Czochralski process; silicon on insulator; thin film transistor; Crystallization; Filters; Integrated circuit technology; Optical films; Semiconductor films; Silicon on insulator technology; Substrates; Surface morphology; Temperature; Thin film transistors;
Conference_Titel :
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-9268-X
DOI :
10.1109/IEDM.2005.1609510
