An extensible FPGA-based postprocessor architecture of timing skew correction for time-interleaved ADCs

An extensible postprocessor architecture of a new algorithm is presented in this paper to correct the timing skew in 7-channel time-interleaved ADCs. The Least Mean Squares (LMS) algorithm is utilized to identify the timing skew, which is used to compensate digital output according to its high order Taylor expansion. FPGA synthesis results show that, with ±0.02Ts timing skew, and normalized input frequency fin/fs=0.47, signal-to-noise-and-distortion ratio and spurious-free dynamic range of the TIADC after calibration reach 85.7dB and 96.8dB, improved by 50dB and 54dB respectively, compared to the uncalibrated digital outputs. The circuit based on the proposed architecture is simple and easily extensive to TIADC with different number of split-ADCs.