DocumentCode
3446033
Title
Ultra-thin-body fully depleted SOI metal source/drain n-MOSFETs and ITRS low-standby-power targets through 2018
Author
Connelly, Daniel ; Clifton, Paul ; Faulkner, Carl ; Grupp, D.E.
Author_Institution
Acorn Technol., Palo Alto, CA
fYear
2005
fDate
5-5 Dec. 2005
Firstpage
972
Lastpage
975
Abstract
Simulations of metal (Schottky) source/drain (S/D) ultra-thin-body fully depleted SOI n-channel MOSFETs, single and dual gate, were performed using parameters associated with ITRS LSTP targets for 2006 through 2018. By optimizing S/D-to-channel underlap for a given S/D barrier height, off-current can be reduced to match the ITRS LSTP specification for each year. ITRS on-current targets then establish limits on the S/D barrier height
Keywords
MOSFET; silicon-on-insulator; ITRS low-standby-power targets; S/D-to-channel underlap optimisation; ultra-thin-body fully depleted SOI metal source/drain n-MOSFET; Acoustic scattering; CMOS technology; Charge carrier processes; FETs; FinFETs; Integrated circuit technology; MOSFET circuits; Phonons; Thermionic emission; Tunneling;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
Conference_Location
Washington, DC
Print_ISBN
0-7803-9268-X
Type
conf
DOI
10.1109/IEDM.2005.1609524
Filename
1609524
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