Title :
Practical finFET design considering GIDL for LSTP (low standby power) devices
Author :
Tanaka, Katsuhiko ; Takeuchi, Kiyoshi ; Hane, Masami
Author_Institution :
Syst. Devices Res. Labs., NEC Corp., Shimokuzawa
Abstract :
Practical design of double-gate undoped-channel FinFET has been investigated through 3D device simulations considering gate-induced drain leakage (GIDL). Optimization of FinFET structure was carried out for hp45 low standby power (LSTP) device (Lg = 25nm). GIDL is reduced by using gradual and offset source/drain (S/D) profile while degradation of drive current is minimized. Through the optimization of lateral spread and offset of S/D profile, the ITRS specifications for drive current and off-state leakage current are achievable by FinFET with 10nm fin width
Keywords :
MOSFET; low-power electronics; semiconductor device models; 10 nm; 3D device simulations; FinFET; GIDL; LSTP; gate induced drain leakage; low standby power devices; Degradation; FinFETs; Immune system; Laboratories; Leakage current; MOSFETs; National electric code; Silicon on insulator technology; Tunneling; Voltage;
Conference_Titel :
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-9268-X
DOI :
10.1109/IEDM.2005.1609526
